1. Field of the Invention
The present invention relates to a microcomputer with a built in flash memory.
2. Description of Related Art
Recently, flash memories have rapidly come onto the market. This is because, unlike EPROM (Erasable Programmable Read-Only Memory) requiring ultraviolet light for erasing, erasure as well as writing of data can be easily achieved electrically with flash memories, and hence the once written program and data (data and the like) can be easily updated. Thus, the microcomputer with a built-in flash memory using the flash memory in place of a mask ROM or EPROM for storing programs or data has also been rapidly extending its markets.
Just as a single chip flash memory not installed into a microcomputer, the flash memory installed in the microcomputer with a built-in flash memory can be written (programmed) and erased using a flash memory writer. While they are mounted on (soldered, connected to) a circuit board, however, the flash memory in the microcomputer with a built-in flash memory or the single chip flash memory cannot be connected to the flash writer, and hence cannot be written or erased by the flash writer. Thus, a microcomputer with a built-in flash memory with a CPU rewritable function is conceived which carries out writing and erasing by transferring data or the like to the flash memory using the CPU of the microcomputer with a built-in flash memory.
In other words, to solve the foregoing problem, a microcomputer with a built-in flash memory with a CPU rewritable function is proposed which can achieve writing and erasing of the flash memory installed in the microcomputer using the embedded CPU even after mounted on a circuit board.
FIG. 8 is a block diagram showing a configuration of a conventional microcomputer with a built-in flash memory with a CPU rewritable function. In this figure, the reference numeral 1 designates a microcomputer, 2 designates an internal bus, 3 designates a CPU with a BIU (Bus-Interface Unit) incorporating an instruction queue buffer 4 designates a flash memory, 5 designates a flash controller, 6 designates a RAM, 7 designates an input/output terminal, 8 designates a clock generator, 9 designates a monitor timer, 10 designates an interrupt controller, 11 designates an external bus, 12 designates a personal computer (called PC from now on), 13 designates an interface (I/F) and 14 designates an oscillator.
FIG. 7 is a block diagram showing an internal configuration of a flash controller 5 of the conventional and of the present invention microcomputer with a built-in flash memory. In this figure, the reference numeral 30 designates a flash writing/erasing executer, 31 designates a flash command register, 32 designates a flash control register, and 32a designates a busy bit in the flash control register 32.
Next, the operation of the conventional microcomputer will be described.
The monitor timer 9 down-counts the clock signal CLK2 the clock generator 8 generates from the oscillation signal supplied from the oscillator 14, and supplies its underflow signal S1 to the interrupt controller 10. Receiving the underflow signal S1, the interrupt controller 10 issues an interrupt request to the CPU 3 by supplying it with a monitor timer interrupt signal S2. The CPU 3 sets a predetermined value to the monitor timer 9 at every fixed time interval using a setting signal S3 so that if the CPU 3 runs away and the monitor timer 9 is not set within the predetermined time period, the monitor timer 9 underflows and generates the monitor timer interrupt signal S2. Detecting the monitor timer interrupt signal S2, the CPU 3 recognizes its own runaway, and returns to its normal operation by executing the corresponding interrupt service routine.
Next, data writing and erasing of the flash memory 4 using the CPU 3 will be described.
It is assumed here that the data to be written is supplied from the PC 12 to the interface 13, and that a program for carrying out the following operations is stored in a particular area of the flash memory 4 or in the RAM 6, and the CPU 3 operates in accordance with the program. When the flash memory 4 stores the program, it must transfer the program to the RAM 6 in advance to execute the program on the RAM 6. This is because the CPU 3 cannot fetch operation code from the flash memory 4 during writing/erasing of the flash memory 4. The transfer of the program to the RAM 6 can present such problems as occupying a memory area on the RAM 6, taking time for transferring the program, and consuming time to develop software.
In the write operation, the CPU 3 writes xe2x80x9c1xe2x80x9d into a CPU rewriting mode designating bit in the flash control register 32 in the flash controller 5, first. In response to this, the flash control register 32 supplies the CPU rewriting mode designating signal S4 to the flash writing/erasing executer 30. The flash writing/erasing executer 30 waits for a command to be written in the flash command register 31. Subsequently, when the CPU 3 writes a write command in the flash command register 31, the flash writing/erasing executer 30 decodes the command, and starts a sequence of writing into the flash memory 4. Then, the CPU 3 reads the data to be written through the interface 13, and writes the data into the flash memory 4. Thus, the flash writing/erasing executer 30 executes actual writing of the data to the flash memory 4 in a prescribed sequence.
In the course of writing to the flash memory 4, the flash writing/erasing executer 30 generates a clock signal and counts it to execute the write process step by step at prescribed time independently of the operation of the CPU 3. Since the CPU 3 can read the write busy signal S5 indicating that the write process is being executed through the busy bit 32a in the flash control register 32, the CPU 3 continues reading the busy bit 32a throughout the course, and waits for the busy signal S5 to be disabled, that is, waits for the end of the write operation.
Assuring that the busy signal S5 is disabled, the CPU 3 verifies whether the data is written into the flash memory 4 correctly by a well known, method. When the data is written correctly, the CPU 3 carries out the next data write in the same manner as described above.
As for the erasure of the flash memory 4, the CPU 3 can execute it by setting a CPU rewriting mode into the flash control register 32 in the flash controller 5, and then by writing an erasing command into the flash command register 31.
Decoding the erasing command, the flash writing/erasing executer 30 executes the erasure of the flash memory 4 in accordance with a prescribed sequence. In the course of erasing the flash memory 4, since the busy signal S5 is enabled, the CPU 3 continues reading the busy bit 32a in the flash control register 32 (polling).
Since the writing and erasing time period is much longer than a common operation period of the PC, the monitor timer 9, which is provided for detecting a runaway of the CPU 3, can underflow, thereby causing an undesired monitor timer interrupt. To prevent the undesired monitor timer interrupt, the CPU 3 must generate the setting signal S3 within a predetermined period to reset the value of the monitor timer 9.
As described above, in the microcomputer with a built-in flash memory, the CPU 3 must execute the polling continuously during the writing/erasing of the flash memory 4 to detect its end. In addition, since the monitor timer 9 continues its operation during the rewriting/erasing of the flash memory 4, an instruction for resetting the value of the monitor timer 9 must be inserted in many places of the program to prevent the underflow of the value of the monitor timer 9.
To solve such a problem, Japanese patent application laid-open No. 10-177563/1998, for example, proposes a new microcomputer with a built-in flash memory. This microcomputer with a built-in flash memory keeps a waiting mode during writing/erasing of the flash memory 4, during which it generates a clock stop signal by ANDing the CPU rewriting mode designating signal S4 and the busy signal S5 output from the flash controller 5. The clock stop signal prevents the clock signal CLK1 from being supplied from the clock generator 8 to the CPU 3, halting the operation of the CPU 3. After completing the writing/erasing of the flash memory 4, the microcomputer returns from its waiting mode, and restarts the supply of the clock signal CLK1, thereby restarting the operation of the CPU 3.
When the waiting mode is released without experiencing the interrupt, instructions queuing at the instruction queue buffer installed in the BIU in the CPU 3 are not cleared. In the course of writing/erasing of the flash memory 4, if the instructions are left queuing at the instruction queue buffer in the BIU when the supply of the clock signal CLK1 to the CPU 3, which is halted by the stop signal, is restarted, the CPU 3 can runaway. Accordingly, the instructions queuing at the instruction queue buffer in the BIU must be cleared when the supply of the clock signal CLK1 to the CPU 3 is restarted after completing the writing/erasing of the flash memory 4. In addition, when supply of the clock signal CLK1 is halted or restarted suddenly without adjusting its timing, an abnormal operation can take place.
In summary, the conventional microcomputer with a built-in flash memory with the foregoing configuration has the following problems.
(1) When rewriting the flash memory 4, it is necessary for the CPU 3 to transfer the control program from the flash memory 4 to the RAM 6 in advance so that the control program is executed on the RAM 6. This presents problems of occupying a memory area on the RAM 6 by the control program, wasting time needed for the transfer, and requires much time for software development.
(2) Since the CPU 3 must continuously execute polling to detect the end of writing/erasing of the flash memory 4, an increasing load is imposed on the software.
(3) Since the monitor timer 9 is operating during rewriting/erasing of the flash memory 4, the instruction for setting the monitor timer value must be inserted in many places in the program, increasing the load on software development.
(4) When restarting the supply of the clock signal CLK1 to the CPU 3, instructions queuing at the instruction queue buffer in the BIU must be cleared each.
(5) If the supply of the clock signal CLK1 is halted or restarted suddenly, an abnormal operation can take place.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a microcomputer with a built-in flash memory capable of reducing a software load in writing/erasing of the flash memory, with lightening a load for developing software.
According to one aspect of the present invention, there is provided a microcomputer with a built-in flash memory comprising: a flash memory for electrically writing or erasing data; a CPU for issuing a writing/erasing command to the flash memory; a monitor timer for producing a time-up signal when the CPU does not set the monitor timer within a predetermined time period; a clock generator for generating a clock signal for operating the CPU; a first interrupt controller for generating a monitor interrupt to the, CPU when the monitor timer outputs the time-up signal; a flash controller for controlling writing/erasing of the flash memory in accordance with the command from the CPU; a waiting mode controller for implementing a waiting mode in response to a CPU rewriting mode designating signal and a busy signal which are output from the flash controller during writing/erasing of the flash memory; and a gate circuit for halting supply of the clock signal from the clock generator to the CPU in the waiting mode in response to a control signal supplied from the waiting mode controller.
Here, the microcomputer with a built-in flash memory may further comprise a particular bit for specifying whether to halt the supply of the clock signal to the CPU, wherein the waiting mode controller implements the waiting mode in response to a value of the particular bit, the CPU rewriting mode designating signal and the busy signal.
The microcomputer with a built-in flash memory may further comprise a one-shot pulse generator for generating a one-shot pulse in response to a change of the busy signal output from the flash controller at an end of writing/erasing of the flash memory; and a second interrupt controller for generating an interrupt signal for releasing the waiting mode in response to the one-shot pulse from the one-shot pulse generator, and for causing an interrupt to the waiting mode controller using the interrupt signal.
The microcomputer with a built-in flash memory may further comprise a changeover switch for switching between the one-shot pulse fed from the one-shot pulse generator and the time-up signal fed from the monitor timer, wherein the first interrupt controller and the second interrupt controller consist of a single common interrupt controller, and wherein the changeover switch supplies its output signal to the common interrupt controller.
The microcomputer with a built-in flash memory may further comprise a logical circuit for generating, from the value of the particular bit and the CPU rewriting mode designating signal, a continuously setting signal that continuously sets the monitor timer when a CPU halting mode is selected in flash memory rewriting operation, and supplies the continuously setting signal to the monitor timer.
The flash controller may comprise a CPU readable flash control register including a particular bit for holding, at an end of writing/erasing of the flash memory, a test resultant signal indicating whether writing/erasing of the flash memory completes normally or abnormally.